1. Field of the Invention
The present invention relates to a gate drive circuit for driving an electrical power switching element.
2. Description of the Related Art
Electrical power converters, to which an electrical power switching element is applied, have steadily expanded an application range thereof with development of the switching element having a larger volume and a higher speed. Recently, among such electrical power switching elements, IGBT and MOSFET, which are MOS gate-type switching elements, have particularly expanded the application range thereof.
The IGBT and MOSFET are non-latching-type switching elements, and which do not maintain on/off states thereof. A major advantage of these non-latching-type switching elements is that high controllability is possible by gate drive as compared with a latching-type switching element such as a thyrister. With these non-latching-type switching elements, even during a switching transition between turning on and turning off, a surge voltage and a surge current can be suppressed by gate control, and a gradient of a current or a voltage during the switching transition can be freely controlled.
Application examples, in which characteristics of such non-latching-type switching element are utilized, include a multi-series high-voltage converter with an active gate drive technology. The multi-series high-voltage converter achieves a high-voltage converter which can be used for a high-voltage usage, such as for an electrical power system, by connecting a number of elements, which have limited withstand pressure, in multi-series connections. In the multi-series converter, there is a problem in large dispersion of voltage-sharing is caused by a slight difference of switching timing among the number of elements serially connected. The active gate driving technology is a counter measure against this problem.
FIG. 1 is a circuit configuration diagram of a conventional gate drive circuit. This gate drive circuit is disclosed in Japanese Patent Application No. 2005-86940. A gate electrode, which is a control input terminal of a switching element 9, is connected to a voltage amplifier 5 through a gate resistor 3, and is also connected to an output of a control current source 6. An input of the control current source 6 is connected to an output of a voltage amplifier 2. A collector-to-emitter voltage of the switching element 9, which is divided by resistors 4a and 4b for dividing a voltage, is applied to the input of the voltage amplifier 2. In a normal operation state, the switching element 9 carries out on/off operations according to a gate signal applied through the voltage amplifier 5. However, in a case where a surge voltage is caused at the time when the switching element 9 is turned off, an output current of the control current source 6 increases. A gate voltage of the switching element 9 rises due to a current flowing from the control current source 6 into a gate terminal of the switching element 9. With this, a collector current of the switching element 9 increases. As a result, a collector voltage of the switching element 9 decreases. With such operation, the surge voltage of the switching element 9 is suppressed.
The gate drive circuit shown in FIG. 1 suppresses generation of the surge voltage by feedback control over a main voltage Vce of the switching element in the gate drive circuit. Such a method does not require any main circuit element except for a switching element. Thus, there is an advantage that a circuit configuration is simple. However, since the switching element needs to share all losses, there is a problem that an element loss increases.
By referring to FIGS. 2 and 3, this problem will be described below in detail.
In FIG. 2, a collector current Ic begins to slightly decline during a period T1. A collector voltage rises in proportion to a time derivative value of the collector current. Accordingly, during the period T1, the collector voltage rapidly rises. When the collector voltage Vce reaches at a certain constant value, an active gate drive circuit for suppressing a peak surge voltage begins the operations, and the collector voltage is controlled to be suppressed at a constant value. This period is defined as a period T2. Since the collector voltage is constant, a time derivative value of the collector current is also a constant value. As a result, the collector current linearly decreases. When the collector current is substantially zero, the period T2 is terminated. During a period T3, the collector current is substantially zero, and the collector voltage rapidly converges to a power supply voltage Vdc.
On the other hand, FIG. 3 shows waveforms of the collector current and of a collector-to-emitter voltage in a case where an active gate is not used. In this case, the period T2 in FIG. 2 is not present. During the period T1, the collector-to-emitter voltage Vce rises in proportion to the time derivative value of the collector current Ic as the collector current Ic decreases. After that, the collector-to-emitter voltage Vce reaches a peak, and rapidly declines when the collector current Ic reaches substantially zero, the collector-to-emitter voltage Vce being a value substantially equal to that of the power supply voltage Vdc. At this time, the period T1 is terminated to proceed to a period T3.
In a case where the active gate drive is not used, a circuit element and control circuit for suppressing the collector-to-emitter voltage Vce, are not present. Accordingly, in a case where inductance of a main circuit is large, the collector-to-emitter voltage exceeds an acceptable maximum value during the period T1 in FIG. 3, and the switching element is broken. An object of applying the active gate drive is to prevent the switching element from being broken with control for suppressing the peak voltage.
In a case where a peak surge voltage is suppressed by the active gate drive technology, an excessive loss is generated during the period of suppressing the surge voltage at the time when the switching element is turned off. The period T2 in FIG. 2 corresponds to the above period. During the period T2, the active gate circuit operates so that the collector voltage can be clamped at a constant value. The collector voltage at the time when the switching element is turned off is proportional to dIc/dt, which is a time derivative value of the collector current Ic. Accordingly, dIc/dt during the period T2, that is, gradient of the collector current Ic is at a constant value. When the collector-to-emitter voltage during this period T2 is defined as Vcep1, a direct current power supply voltage as Vdc, and a component of parasitic inductance of the main circuit as Ls, the following relation is formed.
            V      cepl        -          V      dc        =            -              L        s              ×                  ⅆ                  I          c                            ⅆ        t            
Hence, when it is supposed that an element loss during the period T2 is defined as E2, a time width of the period T2 as t2, a maximum value of the collector current as Icp1, and a tail current is sufficiently small, the following relation is formed.
      E    2    =                    1        2            ⁢              V                  cep          ⁢                                          ⁢          1                    ×              I                  cp          ⁢                                          ⁢          1                    ×              t        2              =                            1          2                ⁢                  V                      cep            ⁢                                                  ⁢            1                          ×                  I                      cp            ⁢                                                  ⁢            1                    2                ×                              L            s                                              V                              cep                ⁢                                                                  ⁢                1                                      -                          V              dc                                          =                        1          2                ⁢                  L          s                ×                  I                      cp            ⁢                                                  ⁢            1                    2                ×                              V                          cep              ⁢                                                          ⁢              1                                                          V                              cep                ⁢                                                                  ⁢                1                                      -                          V              dc                                          
That is, the element loss during the period T2 is proportional to the square of maximum value Icp1 of the collector current. In addition, the element loss dramatically increases as the collector-to-emitter voltage Vcep1 of the turned-off period is closer to the power supply voltage Vdc.